1. Field of the Invention
This invention relates to a semiconductor device comprising a MOS element formed by a salicide technique, in other words, a MOS element in which metal silicide layer is formed over the surfaces of the gate electrode and source/drain regions thereof, and a fabrication method thereof.
2. Field of the Invention
Electronic devices have recently followed a path towards even smaller dimensions, with the aim of creating semiconductor integrated circuits with even greater densities and more sophisticated capabilities. This reduction in dimensions has led to a situation in which there is no option but to achieve narrower widths and shallower depths of impurity diffusion layers that form the source/drain regions (source regions or drain regions) of MOS transistors. However, as the source/drain regions become shallower, the sheet resistance of these impurity diffusion layers rises so far that the channel resistances of the transistors can no longer be ignored and, as a result, the capabilities of the semiconductor integrated circuits are degraded by delays and other problems.
A self-aligned-silicide (salicide) technique is useful for countering these problems. This technique is used to convert the surfaces of the source/drain regions and the gate electrode, which consists of polycrystalline silicon, into a self-aligned silicide, as stated in, for example: LSI Hand-book, edited by The Institute of Electronics and Communication Engineers and published by Ohmsha Ltd., p. 401. Use of the salicide technique makes it possible to lower the resistance of the source/drain regions, as necessitated by even smaller dimensions.
However, it is known that the silicification reaction is suppressed and the sheet resistance increases, either because of the high-density impurities present in the gate electrode and the source/drain regions, particularly that of arsenic used in n-channel MOS transistors, or because of the smaller dimensions necessitated by the narrower widths of the source/drain regions and the gate electrode, as has been disclosed in:
(1) Robert Beyers et. al., J. Appl. Phys. 61 (11) 1987 PA1 (2) Minoru Takahashi et. al., Ext. Abs. 1993 SSDM, p. 458 PA1 (1) Hitoshi Wakabayashi et. al., Technological Research Report SDM95-173 by The Institute of Electronic, Information and Communication Engineers PA1 (2) I. Sakai et. al. Digest 1992 Symposium on VLSI Technology, p. 66 PA1 (A) forming a conductive layer comprising at least silicon on the semiconductor substrate, with an insulating film therebetween; PA1 (B) diffusing impurities to act as donors or acceptors into the semiconductor substrate, to form an impurity diffusion layer for configuring a source region or drain region; PA1 (C) forming a metal layer capable of creating a silicide, on at least the surfaces of the conductive layer and the impurity diffusion layer; and PA1 (D) performing thermal processing to convert the metal layer into a silicide;
A known method of counteracting this problem is to use ion implantation before the silicification, to implant arsenic ions into the surfaces of the source/drain regions and the gate electrode, which consists of polycrystalline silicon, to make the silicon non-crystalline and thus create a low-resistance silicide.
This method is disclosed in:
The technique described by these papers uses a method by which impurities are implanted into the source/drain regions and gate electrode of the transistor to make the semiconductor conductive and, after that impurities are activated, arsenic is implanted therein to make the surfaces of the source/drain regions and gate electrode non-crystalline, and then the silicide layer is formed.
However, according to the technique used to implant the arsenic with the objective of creating the non-crystalline surfaces, if ion implantation is used to bombard the entire surface of the semiconductor substrate with arsenic to make it non-crystalline, that arsenic could cause counter-doping with respect to the layer of diffused p-type impurity, such as boron, so that the density of the p-type impurity in the impurity layer becomes relatively low. In order to prevent this, it is necessary to use a photoresist and pattern it so that the arsenic bombards only the n-type regions. However, this method increases the number of steps and the number of photomasks used for the patterning during ion implantation, leading to an increase in wafer processing costs.